1. Field of the Invention
The present invention relates to a successive approximation A/D converter.
2. Description of the Related Art
As an A/D converter having a medium resolution or high resolution (e.g., 8-bit resolution or more), a successive approximation A/D converter (SAR: Successive Approximation Register) is employed. FIG. 1 is a circuit diagram showing a successive approximation A/D converter 100R. The successive approximation A/D converter 100R includes a sample-and-hold circuit 102, a comparator 104, a logic circuit 106, and a D/A converter 108.
In a sampling phase φ1, the sample-and-hold circuit 102 instructs a sampling capacitor C1 to sample a voltage that corresponds to an input voltage VIN. Subsequently, during a comparison phase φ2, the voltage thus sampled is held. The D/A converter 108 generates a threshold voltage VTH that corresponds to a given digital input DTH. With an N-bit A/D converter, such an arrangement gives rise to a comparison operation being performed N times in the comparison phase φ2. The comparator 104 compares the voltage held by the sample-and-hold circuit 102 with the output voltage VTH of the D/A converter 108 every time the comparison operation is performed. In the first comparison phase φ2, the threshold voltage VTH1 is applied to one end of the sampling capacitor C1, which changes the voltage across the first capacitor C1 to (VIN−VTH1). The comparator 104 compares the voltage (VIN−VTH1) across the first capacitor C1 with a reference voltage (0 V, in this example), so as to judge the magnitude relation between VIN an VTH1.
The logic circuit 106 updates the digital input DTH to be used in the next comparison operation, based on the output of the comparator 104. By repeatedly performing such an operation, such an arrangement generates a digital value DOUT in the form of an N-bit quantized value.
With such a successive approximation A/D converter 100R, a bias power supply 112 is provided in order to set the voltage levels of the inverting input terminal and the non-inverting input terminal of the comparator 104 to optimum voltage levels (see Japanese Patent Application Laid Open No. 2014-138371).
In many cases, the bias power supply 112 is configured as a resistor voltage dividing circuit or a constant voltage source employing diodes or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), for example. Bias switches SW41 and SW42 are turned on during the sampling phase φ1. In this phase, the sampling capacitor C1 is charged using the voltage difference (VIN−VBIAS). Furthermore, a sampling capacitor C2 is charged using the voltage difference −VBIAS. Thus, in the comparison phase, the input voltages of the comparator 104 are biased using the bias voltage VBIAS.
As a result of investigating such a conventional successive approximation A/D converter 100R, the present inventor has come to recognize the following problem.
That is to say, with such a successive approximation A/D converter 100R, a DC bias current IBIAS flows through the bias power supply 112 regardless of the phase thereof even when both the bias switches SW41 and SW42 are turned off. This leads to unnecessary power loss.